1. Field of the Invention:
The present invention relates to a semiconductor apparatus with a through-hole interconnection formed in a semiconductor chip and a method for manufacturing the same.
2. Description of the Related Art:
Heretofore, attention has been given to CSP (chip size package or chip scale package) structure as the miniaturized or thinned structures of semiconductor devices, such as LSIs.
Many of CSPs are provided as ball grid arrays (BGAs) in which balls such as those made of solder are arranged on the uppermost surface of an apparatus or land grid array (LGAs) in which a plurality of flat electrodes are arranged.
In addition, in the case of the CSP technology used in an image sensor, such as a CMOS (complementary metal oxide semiconductor) image sensor or a CCD (charge coupled device) image sensor, an electrode is placed on the backside of a substrate, or the side opposite to the image-sensor side. It is in contrast to the CSP in the past in which an electrode is placed on the principle surface of a substrate (the surface thereof on which an active element is formed).
Such a configuration realizes a miniaturized, thinned semiconductor apparatus to be used for an image sensor.
A ShellOP-type semiconductor, such as one shown in FIG. 1, has been known as a BGA-type CSP used for an image sensor (see, for example, Japanese Unexamined Patent Application Publication No. 2004-165312).
A semiconductor apparatus 100 shown in FIG. 1 has a stacked structure in which a semiconductor chip 109 is sealed with a first glass substrate 101 and a second glass substrate 105 with adhesive layers 104 and 107 made of resin or the like in between.
The semiconductor chip 109 includes a semiconductor substrate 111 and a wiring layer 110. The semiconductor substrate 111 is made of silicon or the like on which a transistor, a protective film, and the like, not shown in the figure, are formed. The wiring layer 110 is formed on the semiconductor substrate 111 and includes stacked layers of conductive layers and insulating layers. The conductive layers include wiring, pad electrodes, and the like. The insulating layers are insulating interlayers or the like that covers the conductive layers.
In addition, the semiconductor chip 109 is provided with a light-receiving/emitting element, a light-receiving/emitting sensor surface (not shown) and the like. In addition, a color filter and an on-chip lens (not shown) corresponding to the sensor surface are formed above the wiring layer 110.
Furthermore, in the semiconductor apparatus 100, the semiconductor chip 109 is connected to a rewiring layer 108 through a pad electrode in the wiring layer 110. Then, the semiconductor chip 109 is rewired by connecting the end of the rewiring layer 108 to the wiring layer 103 of the semiconductor apparatus 100.
In the semiconductor apparatus 100, the wiring layer 103 is formed from the boundary of the first glass substrate 101 and the adhesive layer 107, which are stacked on top of one another, to the lower part of the second glass substrate 105 through the lateral sides of the semiconductor chip 109, the adhesive layer 104, and the second glass substrate 105. Further, the wiring layer 103 is connected to an external terminal 106 of the semiconductor apparatus 100 at the lower part of the second glass substrate 105.
Furthermore, for example, a protective layer 102 made of an insulating resin such as a solder resist covers the whole surface, except the surface of the external terminals 106. A resin layer 112 is formed between the wiring layer 103 and the second glass substrate 105, at a position corresponding to the position where the external terminal 106 is formed. The resin layer 112 is a member for reducing the stress on the external terminal 106.
After the protective layer 102 is formed, the semiconductor apparatus 100 is separated into pieces in the direction shown by arrows C and C′. Therefore, cutting ends 113 of the wiring layer 103 are exposed without being covered with the protective layer 102. With the ends of the wiring layer 103 exposed on the lateral surface of the semiconductor apparatus 100, the wiring layer 103 may be corroded by reacting with moisture in the atmosphere. It may lead the semiconductor apparatus 100 unreliable in operation.
Furthermore, a part where the rewiring layer 108 and the wiring layer 103 are connected has a small contact area. Thus, contact resistance may increase and disconnection may occur, for example.
In addition to the aforementioned ShellOP-type semiconductor apparatus, a semiconductor apparatus having a different structure is used as an image sensor in the art, in which a through-hole interconnection is formed inside the cutting plane of a semiconductor substrate (see, for example, Japanese Unexamined Patent Application Publication No. 2006-128353 and Dzafir Shariff, et al., “Via Interconnections for Wafer Level Packaging: Impact Tapered Via Geometry on Product Yield and Reliability” 2007 Electronic Components and Technology Conference).
FIG. 2 is a cross-sectional view illustrating a through-hole interconnection 206 formed in a semiconductor substrate 210 and the surrounding structure thereof in a semiconductor apparatus 200.
In the semiconductor apparatus 200, a semiconductor chip 203 is bonded to a supporting substrate 201, which is a light-transmitting substrate such as a glass substrate, with a resin layer 208 in between.
The semiconductor chip 203 includes a semiconductor substrate 210 and a wiring layer 209. The semiconductor substrate 210 is made of silicon or the like on which a transistor, a protective film, and the like, not shown in the figure, are formed. The wiring layer 209 is formed on the semiconductor substrate 210 and includes stacked layers of conductive layers and insulating layers. The conductive layers include wiring, a pad electrode 202, and the like. The insulating layers are insulating interlayers or the like that covers the conductive layers.
In addition, the semiconductor chip 203 is provided with a light-receiving/emitting element, a light-receiving/emitting sensor surface (not shown) and the like. In addition, a color filter and an on-chip lens (not shown) corresponding to the sensor surface are formed above the wiring layer 209.
In the semiconductor chip 203, furthermore, the through-hole interconnection 206 is formed through the semiconductor substrate 210 and connected to the pad electrode 202. The through-hole interconnection 206 is made by forming a via hole toward the pad electrode 202 formed in the wiring layer 209 from the side opposite to a side on which the wiring layer 209 of the semiconductor substrate 210 is formed and by covering the inside of the via hole with a conductive layer 205. Here, the conductive layer 205 is formed from the pad electrode 202 to the lower part of the semiconductor substrate 210 through the through-hole interconnection 206. The conductive layer 205 is connected to an external terminal 207 of the semiconductor apparatus 200 at the lower part of the semiconductor substrate 210.
In addition, an insulating layer 204 is formed between the semiconductor substrate 210 and the conductive layer 205 in the semiconductor apparatus 200. A protective layer 217 made of an insulating resin such as a solder resist covers the whole surface, except the portion where the conductive layer 205 and the external terminal 207 are connected.
Moreover, a resin layer 211 is formed between the conductive layer 205 and the insulating layer 204, at a position corresponding to the position where the external terminal 107 is formed. The resin layer 211 is a member for reducing the stress on the external terminal 207.
Next, a method for forming the through-hole interconnection 206 of the semiconductor apparatus 200 shown in FIG. 2 will be described.
FIG. 3A illustrates the semiconductor substrate 210 and the wiring layer 209 formed thereon in the semiconductor chip 203 in a state before the formation of the through-hole interconnection 206. As shown in FIG. 3A, the semiconductor apparatus 200 shown in FIG. 2 is represented upside down.
The wiring layer 209 is formed by stacking a plurality of insulating layers 212 and a plurality of wiring lines 213. In addition, the pad electrode 202 for interconnecting the external terminal and the semiconductor chip 203 is formed in the wiring layer 209.
Next, for example, a resist pattern or the like is formed on the semiconductor chip 203 using photolithography and the semiconductor chip 203 is then subjected to a dry-etching process. As shown in FIG. 3B, an opening 214 for a via hole is formed in the semiconductor chip 203.
At this time, electric charges are accumulated on the surface of the insulating layer 212 when the semiconductor substrate 210 is dry-etched. Accordingly, the etching is carried out in the lateral direction near the boundary between the semiconductor substrate 210 and the insulating layer 212. Therefore, side etching is locally carried out on the side of the semiconductor substrate 210 near the boundary between the semiconductor substrate 210 and the insulating layer 212. Thus, a V-shaped recessed portion 215 or a notch is formed.
Subsequently, the insulating layer 212 exposed to the opening 214 of the semiconductor substrate 210 is etched to expose the pad electrode 202. As a result, as shown in FIG. 4C, a via hole 216 is formed through the semiconductor substrate 210 to the pad electrode 202. At this time, at a position corresponding to the recessed portion 215 formed in the semiconductor substrate 210, the insulating layer 212 is also subjected to the side etching process. Thus, the recessed portion 215 is also formed in the insulating layer 212.
Next, as shown in FIG. 4D, the insulating layer 204 is formed to cover both the semiconductor substrate 210 and the wiring layer 209 in the via hole 216. The coverage of the insulating layer 204 on the surface of the semiconductor substrate 210, the coverage thereof on the lateral surface inside the via hole 216, and the coverage thereof on the bottom surface of the via hole 216 are different from each other. Thus, the insulating layer 204 is formed thick on the semiconductor substrate 210 and thin on the pad electrode 202 and on the wall near the bottom of the via hole 216. Furthermore, the insulating layer 204 in the via hole 216, which is thinly formed, is removed from the pad electrode 202 by etching. As a result, part of the pad electrode 202 is exposed as shown in FIG. 5E. In this case, in other words, only the insulating layer 204 on the bottom of the via hole 216 can be removed using the difference in the coverage without using any mask or the like.
Subsequently, after the formation of a barrier metal and a seed metal (not shown), as shown in FIG. 5F, the exposed pad electrode 202 is rewired to form the conductive layer 205 connected to the external terminal 207 of the semiconductor apparatus 200.
Subsequently, the protective layer 217 is formed on the part of the conductive layer 205 other than the portion where the external terminal 207 is formed. As a result, the through-hole interconnection 206 of the semiconductor apparatus 200 as shown in FIG. 2 can be formed.
Alternatively, there is another method for forming a through-hole interconnection on a semiconductor substrate to avoid the formation of a recessed portion or a notch, in the boundary between the aforementioned semiconductor substrate and the insulting layer on the semiconductor (see, for example, P. R. Morrow, et al., “Three-Dimensional Wafer Stacking Via Cu—Cu Bonding Integrated With 65-nm Strained-Si/Low-k CMOS Technology” IEEE Electron Device Letters, Vol. 27, No 5, MAY 2006). In this method, the process of etching a semiconductor substrate to form a via hole through both the semiconductor substrate and the insulating layer is divided into two or more steps.
For example, the process has two divided steps of etching the semiconductor substrate. As shown in FIG. 6A, first, etching of the semiconductor substrate 210 is carried out at a high etching rate to form part of an opening 218a to be provided as a via hole in the semiconductor substrate 210 and the insulating layer 212. Subsequently, the etching of the semiconductor substrate 210 is carried out at a low etching rate to etch the semiconductor substrate 210 to the boundary with the insulating layer 212 as shown in FIG. 6B.
At this time, the angle of the internal surface of the opening 218a is changed at the position where the first step of etching the semiconductor substrate 210 is switched to the second step, resulting in a tapered opening 218a. 
Furthermore, as shown in FIG. 7C, the pad electrode 202 is partially exposed by etching the insulating layer 212. A via hole 218 is formed through the semiconductor substrate 210 and the insulating layer 212. Subsequently, as shown in FIG. 7D, the insulating layer 204 is formed on the surfaces of the semiconductor substrate 210 and the via hole 218 as shown in FIG. 7D and the conductive layer 205 connecting to the pad electrode 202 is then formed.
After that, the semiconductor apparatus 200 with the through-hole interconnection 206 as shown in FIG. 2 can be completed by forming a protective film, an external terminal, and the like.
According to the method, etching is carried out at a low etching rate when etching near the boundary between the insulating layer and the semiconductor substrate to suppress the formation of a recessed portion. In addition, the initial etching of the semiconductor substrate is carried out at a high etching rate, thereby producing a semiconductor apparatus without lowering the rate of forming a via hole.